The present invention relates to a half tone display driving circuit for a crystal matrix panel and a half tone display method therefor.
In a conventional half tone display driving circuit for a crystal matrix panel, as described in JP-A-50-156396, the half tone display is effected by changing the time duration of application of voltages to a signal line and a scanning line of the liquid crystal matrix panel to change effective voltage applied to the liquid crystal. When in this conventional method the number of points at which half tone of the same degree is displayed is large, the frequency of voltage switching operations effected simultaneously on signal lines increases and noises are induced scanning lines by way of the liquid crystal, raising a problem that the effective voltage applied to the liquid crystal is decreased to decrease brightness of display.
The half tone display driving circuit for a crystal matrix panel will be detailed with reference to FIGS. 2 to 17.
FIG. 2 shows an example of a liquid crystal display apparatus having ability to display half tone.
Referring to FIG. 2, reference numeral 1 designates display data, 2 a shift clock serving as a synchronization clock for the display data 1, and 3 a horizontal clock for defining the interval of one horizontal period. Reference numeral 4 designates a display data shift register for storing an amount of data pieces of display data 1 for one horizontal period and reference numeral 5 generally represents horizontal display data pieces Dl to Dn contained in the display data 1 for one horizontal period stored in the display data shift register 4. Reference numeral 6 designates a decoder and 7 generally represents sets of data pieces D.sub.11 D.sub.12 D.sub.13 to Dn.sub.1 Dn.sub.2 Dn.sub.3 which are delivered out of the decoder 6 to serve as select signals. Reference numeral 8 represents a clock GCLK which has two cycles within one horizontal period. Reference numeral 9 designates a 1/2 pulse generator for generating a pulse the duration of which is half of one horizontal period and 10 a 1/2 duration pulse (hereinafter simply referred to as 1/2 pulse) delivered out of the 1/2 pulse generator. Reference numeral 11 designates a selector and 12 generally represents output signals Xl to Xn of the selector 11 which serve as column selection signals. Reference numeral 13 designates a line head clock and 14 a vertical shift register which receives the line head clock 13 to shift the data in accordance with the horizontal clock 3. Reference numeral 15 generally represent output signals Yl to Ym of the vertical shift register 14 which serve as line or row selection signals. Reference numeral 16 designates a voltage Va and 17 a voltage Vb, the Va and Vb voltages 16 and 17 being positive and the former being higher than the latter. Reference numerals 18 designates a column liquid crystal driver, 19 generally represents output signals V.sub.xl to V.sub.xn of the column liquid crystal driver 18 which serve as column driving signals. Reference numeral 20 designates a line or row liquid crystal driver and 21 generally represents output signals V.sub.yl V.sub.ym of the row liquid crystal driver 20 which serve as row driving signals. Denoted by 22 is a liquid crystal panel.
FIG. 4 shows the interior of the decoder 6 in which decoders 23 are provided.
FIG. 5 shows a truth table of the decoder 23.
FIG. 6 shows an internal circuit of 1/2 pulse generator 9 including a NOT circuit 24 for clock, a NOT circuit 25 for resetting, a D flip-flop with resetting 26 and a D flip-flop 27.
FIG. 7 is a timing chart for the 1/2 pulse generator 9.
FIG. 8 shows an internal circuit of selector 11 including n stages each having AND circuits 28 to 30 and an OR circuit 31.
FIG. 9 is a timing chart of the operation of the vertical shift register 14.
FIG. 10 shows an internal circuit of column liquid crystal driver 18 including n stages each having a switching transistor 32 for Va, a switching transistor 33 for Vb and a NOT circuit 34.
FIG. 11 is a timing chart of the operation of the column liquid crystal driver 18.
FIG. 12 is a timing chart of the operation of the FIG. 2 apparatus.
FIG. 13 shows waveforms including those applied to the liquid crystal panel 22 when the FIG. 2 apparatus is operated at timings shown in FIG. 12.
FIG. 14 is a diagram useful in explaining the operational principle of the liquid crystal panel 22.
FIG. 15 is an equivalent circuit of the liquid crystal panel 22.
FIG. 16 shows a charging waveform appearing at a normal display point of the liquid crystal panel 22.
FIG. 17 shows a charging waveform appearing at a half tone display point of the liquid crystal panel 22.
The operation of the FIG. 2 apparatus will now be explained.
As shown in the timing chart of FIG. 3 data pieces of display data 1 inputted in synchronism with the shift clock 2 during one horizontal period ranging from a fall edge of the horizontal clock 3 to the succeeding fall edge thereof are fetched sequentially by the display data shift register 4. During the succeeding horizontal display period, a data piece, of the display data 1 fetched during the preceding horizontal display period, which is fetched at time t.sub.1 (see FIG. 12) is delivered as output signal D1 of the horizontal display data 5, a data piece fetched at time t.sub.2 is delivered as output signal D2, a data piece fetched at time t.sub.3 is delivered as output signal D3 and similarly a data piece fetched at time tn is delivered as output signal Dn.
The decoder 6 receives the horizontal display data and decodes the data pieces Dl to Dn into sets of D.sub.11 D.sub.12 D.sub.13 to Dn.sub.1 Dn.sub.2 Dn.sub.3 which are delivered out of the decoder 6 as select signals 7.
As shown in FIG. 4, the decoder 6 includes the n decoders 23 which receive respectively one, Dj, of the data pieces Dl to Dn of the horizontal display data 5 and delivers one, Dj.sub.1 Dj.sub.2 Dj.sub.3, of the sets D.sub.11 D.sub.12 D.sub.13 to Dn.sub.1 Dn.sub.2 Dn.sub.3 of the select signals 7 in accordance with the truth table shown in FIG. 5.
As shown in FIG. 6, the 1/2 pulse generator 9 includes the NOT circuits 24 and 25, D flip-flop with resetting 26 and D flip-flop 27.
In operation, the 1/2 pulse generator responds to the GCLK 8 and horizontal clock 3 to generate a 1/2 pulse 10 which has the first half of "high" and the second half of "low" during one horizontal period, as shown in the timing chart of FIG. 7.
The selector 11 responds to the sets D.sub.11 D.sub.12 D.sub.13 to Dn.sub.1 Dn.sub.2 Dn.sub.3 of the select signals 7 to selectively deliver "high" signal, 1/2 pulse 10 or "low" signal as individual output signals Xl to Xn of the column selection signals 12.
As shown in FIG. 8, the selector 11 includes n stages each having the three AND circuits 28 to 30 and the one OR circuit 31. Each stage operates to produce "low" signal as output signal Xj when Dj.sub.1 "high", 1/2 pulse 10 as output signal Xj when Dj.sub.2 is "high", and "high" signal as output signal Xj when Dj.sub.3 is "high". A set of Dj.sub.1 Dj.sub.2 Dj.sub.3 representative of output signals of the decoder 6 always contain only one "high" signal as will be seen from the FIG. 5 truth table of the decoder 6.
As shown in FIG. 10, the column liquid crystal driver 18 includes n stages each having the NOT circuit 34, Va switching transistor 32 and Vb switching transistor 33. The driver 18 is responsive to the column selection signals Xl to Xn to produce on output leads output signals Vx.sub.l to Vx.sub.n of the column driving signal 19, thereby providing voltages for driving the liquid crystal. The column liquid crystal driver 18 operates, as shown in FIG. 11, to deliver the voltage Va as output signal Vxj of column driving signals 19 which corresponds to one, Xj, of the column selection signals Xl to Xn when the input signal Xj is "1" but deliver the voltage Vb when the input signal Xj is "0".
The vertical shift register 14 operates, as shown in FIG. 9, to fetch a line head clock 13 at the timing of a fall edge of the horizontal clock 3 and deliver an output signal Y1 of the row selection signals 15 and thereafter it operates to shift to sequential delivery of output signals Y2, Y3, - - - Ym in synchronism with fall edges of the horizontal clock 3.
The row liquid crystal driver 20 structurally resembles the column liquid crystal driver 18 and operates to deliver -Va to V.sub.Yk', one of output signals V.sub.Yl to V.sub.Ym to of row driving signals 21 which corresponds to Y.sub.k, one of signals Yl to Ym of the row selection signal 15 when the Yk is "1" but deliver Vb when the Yk is "0".
The apparatus of FIG. 2 operates as shown in the operational timing chart of FIG. 12 when the input signal 1 contains data pieces "0", "1" and "2".
The data pieces "0", "1" and "2" of the input signal 1 sequentially inputted, beginning with a fall edge of a horizontal clock signal 3, are delivered as output signals D1, D2 and D3 of the horizontal display data 5 at the timing of a fall edge of the succeeding horizontal clock signal 3.
The horizontal display data 5 is decoded by the decoder 6 and select signals 7 are delivered therefrom which cause the selector 11 to select "high"signal, 1/2 pulse 10 or "low" signal so as to produce column selection signals 12 containing signal X1 of "low" level, signal X2 of 1/2 pulse 10 and signal X3 of "high" level.
The column liquid crystal driver 18 receives the column selection signals 12 to produce Vb as signal Vx.sub.1, Va and Vb as signal Vx.sub.2 during the first and second halves of one horizontal period, respectively, and Va as signal Vx.sub.3.
On the other hand, the vertical shift register 14 receives the line head clock which rises during a horizontal period, within which the input signal 1 containing data pieces "0", "1" and "2" is inputted, and does not rise during the succeeding horizontal period. The line head clock is then latched by a fall edge of the horizontal clock signal to provide a "high" signal Y1 of the row selection signals 15. This "high" signal Y1 causes the row liquid crystal driver 20 to produce-Va as signal V.sub.Y1 of the row driving signal 21 and Vb as the other signals V.sub.Y2 V.sub.Y3, - - - of the row driving signal 21.
When the apparatus operates at timings shown in FIG. 12, voltages are applied to the liquid crystal panel 22 at timings as shown in FIG. 13.
The liquid crystal panel 22 is constructed as shown in FIG. 14 and operates to transmit light when the potential difference between row driving signal 21 and column driving signal 19 is large (here, greater than Va-Vb) but intercept light when the potential difference is small (here, less than Va-Vb). Electrically, the liquid crystal has characteristics of capacitor, as shown in FIG. 15. Therefore, for V.sub.X3 -V.sub.Y1 in FIG. 13, the liquid crystal is charged during one horizontal period as shown in FIG. 16. However, for V.sub.X2 -V.sub.Y1 in FIG. 13, the liquid crystal is charged only during the first half of one horizontal period, with the result that the liquid crystal is not charged fully as shown in FIG. 17 to slightly transmit light, thereby effecting display of half tone.
Through the above operation, the half tone display can be accomplished.
Conventionally, the half tone display is realized by changing the pulse width but disadvantageously, with the number of the half tone display points of the same degree increased, noises are generated by simultaneous changes at edges of pulse signals to decrease brightness of display.
A decrease in brightness will now be explained with reference to FIGS. 18 to 20.
FIG. 18 shows waveforms ideally appearing when the half tone display is effected over a wide area of the liquid crystal panel 22.
FIG. 19 shows waveforms actually appearing when the half tone display is effected over the wide area of the liquid crystal panel 22.
FIG. 20 shows charging waveforms obtained with waveforms of FIGS. 18 and 19.
When the half tone display is effected over the wide area of the liquid crystal panel 22 in the FIG. 2 apparatus, the brightness is decreased as will be described below.
As shown in FIG. 18, data pieces "1" of display data 1 are sequentially inputted. Then, Va and Vb are produced as each of the signals V.sub.Xl to V.sub.Xn during the first and second halves of one horizontal period, respectively. On the other hand, the vertical shift register 14 first receives the line head clock 13 and thereafter shifts to sequentially produce-Va as either one of signals V.sub.Yl to V.sub.Ym of the row driving signal 21 in synchronism with fall edges of the horizontal clock signals 3.
Through the above operation, voltage V.sub.Xl -V.sub.Yl in FIG. 18 is applied to a crossing on the first row and the first column of the liquid crystal panel 22.
Practically, however, in the liquid crystal panel 22 having an electrical equivalent circuit as shown in FIG. 15, AC components are generated from all of the column driving signals 19 at voltage switching points to induce noises in the row driving signals 21, as shown in FIG. 19.
Consequently, the rise of the voltage applied to the liquid crystal of the liquid crystal panel gets blunted as shown at the righthand illustration in FIG. 20, with the result that the effective voltage applied to the liquid crystal panel 22 is decreased to decrease the brightness of display.